The present invention relates generally to projection exposure methods and apparatuses used to expose an object, such as a single crystal substrate or a spherical semiconductor for a semiconductor wafer, and a glass plate for a liquid crystal display (“LCD”) in photolithography, and more particularly to a method for optimizing one or more values of device parameter(s). Here, the “device parameter” is a parameter which may be set in an exposure apparatus, defines an exposure condition, an illumination condition of an alignment optical system, etc., and is relevant to an alignment between a reticle and the object to be exposed. The inventive exposure method and apparatus are suitable for precise and prompt alignments under circumstances where Wafer Induced Shift (“WIS”) as a wafer process error may occur.
Projection exposure apparatuses used to manufacture semiconductor devices have been required to expose a circuit pattern on a reticle onto a wafer at high resolution along with fine and high-density circuits. The projection resolving power of a circuit pattern depends upon a numerical aperture (“NA”) of a projection optical system and a wavelength of exposure light, and methods to achieve high resolution include a method to increase an NA of a projection optical system and a method to use exposure light having a shorter wavelength. Regarding the latter method, an exposure light source has shifted from g-line to i-line and from i-line to the excimer laser. Exposure apparatuses that use the excimer laser having an oscillation wavelength of 248 nm and 193 nm have already been reduced to practice. At present, those exposure methods have been currently studied for the next generation, which use vacuum ultraviolet (“VUV”) having a wavelength of 157 nm and extreme ultraviolet (“EUV”) having 13 nm.
Manufacture processes of semiconductor devices are diversified, and the planation technology for solving a problematically small depth of focus in an exposure apparatus have called attention, such as a Tungsten Chemical Mechanical Polishing (“W-CMP”) process, Cu dual damocene wiring technology, and technology that applies a low dielectric constant (“Low-k”) material to an interlayer dielectric.
There have been proposed a wide variety of structures and materials for semiconductor devices, for example, Pseudomorphic High Electron Mobility Transistor (“P-HEMT”) and Metamorphe-HEMT (“M-HEMT”) made of compound such as GaAs and InP, Heterojunction Bipolar Transistors (“HBTs”) that use SiGe, SiGeC, etc.
On the other hand, fine circuit patterns have required a precise alignment between a reticle (mask) that forms a circuit pattern and a wafer to which the circuit pattern is projected; the necessary precision is ⅓ of a circuit critical dimension, e.g., 60 nm that is ⅓ as long as the current design width of 180 nm.
Alignment in an exposure apparatus is usually carried out by imaging an optical image of an alignment mark formed on a wafer, onto an image pickup device, such as a CCD camera, and by image-processing an electric signal to detect a position of the mark on the wafer. In general, a non-uniform film thickness of resist near the alignment mark and an asymmetric shape of the alignment mark are influential factors that deteriorate alignment accuracy on the wafer upon alignment between the reticle and wafer. These alignment error factors caused by the wafer are referred to as WIS.
In the existing circumstances of the semiconductor industry, there are many device parameters to be set in exposure apparatuses according to types of exposure methods and products. In addition, these parameters are not independent but closely related to each other. An operator of an exposure apparatus in a device manufacturer has conventionally determined these device parameter values by trial and error, and spent a large amount of time in determining optimal parameter values. Even after the device parameters values have been determined, they often need to be reset when a process error occurs and the device parameter values need to change in accordance with changes of manufacture processes corresponding to the process error. This also requires a large amount of time.
According to the current optimization of the device parameter values, several tentative wafers are exposed and these values are determined as offsets based on a result from an overlay detector. Therefore, the present optimization is disadvantageously less responsive to process variance.
Of course, in manufacturing semiconductor devices, a manufacturing apparatus has a limited time from turning on to starting mass production, and therefore a limited time to determine these device parameter values. In addition, it is necessary to improve the operation time of the manufacture apparatus viewed from Cost of Ownership (“CoO”), and thus the device parameter values should be varied promptly. In this context, it is very difficult to manufacture a wide variety of semiconductor devices with optimal parameter values. When the alignment is not optimized, the parameter values are not optimized, and the manufacture apparatus, which would otherwise provide high yield, can provide only insufficient yield, causing deterioration of yield. This deterioration of yield would cause increased manufacture cost, lowered pack, and weakened the manufacturer's competitive power.